Buffered And Unbuffered Gates

One decided disadvantage of CMOS is slow speed, as compared to TTL. The input capacitances
of a CMOS gate are much, much greater than that of a comparable TTL gate { owing to the use of
MOSFETs rather than BJTs { and so a CMOS gate will be slower to respond to a signal transition
(low-to-high or visa-versa) than a TTL gate, all other factors being equal. The RC time constant
formed by circuit resistances and the input capacitance of the gate tend to impede the fast rise- and
fall-times of a digital logic level, thereby degrading high-frequency performance.

A strategy for minimizing this inherent disadvantage of CMOS gate circuitry is to "buffer" the
output signal with additional transistor stages, to increase the overall voltage gain of the device.
This provides a faster-transitioning output voltage (high-to-low or low-to-high) for an input voltage
slowly changing from one logic state to another. Consider this example, of an "unbuffered" NOR
gate versus a "buffered," or B-series, NOR gate:

CMOS unbuffered NOR Gate


"B-series" (buffered) NOR gate

"B-series" (buffered) NOR gate

In essence, the B-series design enhancement adds two inverters to the output of a simple NOR
circuit. This serves no purpose as far as digital logic is concerned, since two cascaded inverters
simply cancel:

Keywords : Nand, Gate, Cmos, OR, Buffered And Unbuffered Gates, CMOS-gates, Logic Gate, Create, TTL, Transistor, RC, High, Low, Logic, High-to-low, Low-to-highBJT, MOSFET
Writer : delon  |
26 Nov 2006 Mon   
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