This schematic illustrates a real circuit, but it isn't called a "two-input inverter." Through
analysis we will discover what this circuit's logic function is and correspondingly what it should be
designated as.
Just as in the case of the inverter and bu®er, the "steering" diode cluster marked "Q
emitters, and in the circuit it looks like this:
In the single-input (inverter) circuit, grounding the input resulted in an output that assumed the
"high" (1) state. In the case of the open-collector output con¯guration, this "high" state was simply
"°oating." Allowing the input to °oat (or be connected to V
cc) resulted in the output becoming
grounded, which is the "low" or 0 state. Thus, a 1 in resulted in a 0 out, and visa-versa.
Since this circuit bears so much resemblance to the simple inverter circuit, the only di®erence
being a second input terminal connected in the same way to the base of transistor Q
2, we can say
that each of the inputs will have the same e®ect on the output. Namely, if either of the inputs are
grounded, transistor Q
2 will be forced into a condition of cuto®, thus turning Q3 o® and °oating the
output (output goes "high"). The following series of illustrations shows this for three input states
(00, 01, and 10):
Input
A =0
Input
B =0
Output =1
Input
A =0
Input
B =1
Output =1
Input
A =1
Input
B =0
Output =1
In any case where there is a grounded ("low") input, the output is guaranteed to be °oating
("high"). Conversely, the only time the output will ever go "low" is if transistor Q
3 turns on, which
means transistor Q
2 must be turned on (saturated), which means neither input can be diverting R1
current away from the base of Q
2. The only condition that will satisfy this requirement is when
both inputs are "high" (1):
Input
A =1
Input
B =1
Output =
0
Collecting and tabulating these results into a truth table, we see that the pattern matches that
of the NAND gate:
In the earlier section on NAND gates, this type of gate was created by taking an AND gate and increasing its complexity by adding an inverter (NOT gate) to the output. However, when we examine this circuit, we see that the NAND function is actually the simplest, most natural mode of operation for this TTL design. To create an AND function using TTL circuitry, we need to
increase the complexity of this circuit by adding an inverter stage to the output, just like we had to add an additional transistor stage to the TTL inverter circuit to turn it into a buffer:
The truth table and equivalent gate circuit (an inverted-output NAND gate) are shown here:
Of course, both NAND and AND gate circuits may be designed with totem-pole output stages
rather than open-collector. I am opting to show the open-collector versions for the sake of simplicity.