CMOS Gate Circuitry

CMOS gate circuitry

Up until this point, our analysis of transistor logic circuits has been limited to the TTL design
paradigm, whereby bipolar transistors are used, and the general strategy of floating inputs being
equivalent to "high" (connected to Vcc) inputs { and correspondingly, the allowance of "open-
collector" output stages { is maintained. This, however, is not the only way we can build logic

Field-efect transistors, particularly the insulated-gate variety, may be used in the design of gate
circuits. Being voltage-controlled rather than current-controlled devices, IGFETs tend to allow very
simple circuit designs. Take for instance, the following inverter circuit built using P- and N-channel

Inverter Circuit Using IGFETs

Notice the "Vdd" label on the positive power supply terminal. This label follows the same
convention as "Vcc" in TTL circuits: it stands for the constant voltage applied to the drain of a
field effect transistor, in reference to ground.

Let's connect this gate circuit to a power source and input switch, and examine its operation.
Please note that these IGFET transistors are E-type (Enhancement-mode), and so are normally-off
devices. It takes an applied voltage between gate and drain (actually, between gate and substrate)
of the correct polarity to bias them on.

The upper transistor is a P-channel IGFET. When the channel (substrate) is made more positive
than the gate (gate negative in reference to the substrate), the channel is enhanced and current is
allowed between source and drain. So, in the above illustration, the top transistor is turned on.
The lower transistor, having zero voltage between gate and substrate (source), is in its normal
mode: off. Thus, the action of these two transistors are such that the output terminal of the gate
circuit has a solid connection to Vdd and a very high resistance connection to ground. This makes
the output "high" (1) for the "low" (0) state of the input.
Next, we'll move the input switch to its other position and see what happens:

Now the lower transistor (N-channel) is saturated because it has sufficient voltage of the correct
polarity applied between gate and substrate (channel) to turn it on (positive on gate, negative on
the channel). The upper transistor, having zero voltage applied between its gate and substrate, is
in its normal mode: off. Thus, the output of this gate circuit is now "low" (0). Clearly, this circuit
exhibits the behavior of an inverter, or NOT gate.

Using field-effect transistors instead of bipolar transistors has greatly simplified the design of
the inverter gate. Note that the output of this gate never °oats as is the case with the simplest
TTL circuit: it has a natural "totem-pole" con¯guration, capable of both sourcing and sinking load
current. Key to this gate circuit's elegant design is the complementary use of both P- and N-channel
IGFETs. Since IGFETs are more commonly known as MOSFETs (Metal-Oxide-Semiconductor
Field Effect Transistor), and this circuit uses both P- and N-channel transistors together, the
general classification given to gate circuits like this one is CMOS: Complementary Metal Oxide

CMOS circuits aren't plagued by the inherent nonlinearities of the field-effect transistors, because
as digital circuits their transistors always operate in either the saturated or cutooff modes and never
in the active mode. Their inputs are, however, sensitive to high voltages generated by electrostatic
(static electricity) sources, and may even be activated into "high" (1) or "low" (0) states by spurious
voltage sources if left °oating. For this reason, it is inadvisable to allow a CMOS logic gate input
to °oat under any circumstances. Please note that this is very different from the behavior of a TTL
gate where a °oating input was safely interpreted as a "high" (1) logic level.
This may cause a problem if the input to a CMOS logic gate is driven by a single-throw switch,
where one state has the input solidly connected to either Vdd or ground and the other state has the
input °oating (not connected to anything)

Also, this problem arises if a CMOS gate input is being driven by an open-collector TTL gate.
Because such a TTL gate's output °oats when it goes "high" (1), the CMOS gate input will be left
in an uncertain state:

Fortunately, there is an easy solution to this dilemma, one that is used frequently in CMOS
logic circuitry. Whenever a single-throw switch (or any other sort of gate output incapable of both
sourcing and sinking current) is being used to drive a CMOS input, a resistor connected to either
Vdd or ground may be used to provide a stable logic level for the state in which the driving device's
output is floating. This resistor's value is not critical: 10 k­ is usually sufficient. When used to
provide a "high" (1) logic level in the event of a °oating signal source, this resistor is known as a
pullup resistor :

When such a resistor is used to provide a "low" (0) logic level in the event of a floating signal
source, it is known as a pulldown resistor. Again, the value for a pulldown resistor is not critical:

Because open-collector TTL outputs always sink, never source, current, pullup resistors are
necessary when interfacing such an output to a CMOS gate input:

Although the CMOS gates used in the preceding examples were all inverters (single-input), the
same principle of pullup and pulldown resistors applies to multiple-input CMOS gates. Of course, a
separate pullup or pulldown resistor will be required for each gate input:

Pullup resistors for a 3-input CMOS AND gate

Pullup resistors for a 3-input CMOS AND gate

This brings us to the next question: how do we design multiple-input CMOS gates such as AND,
NAND, OR, and NOR? Not surprisingly, the answer(s) to this question reveal a simplicity of design
much like that of the CMOS inverter over its TTL equivalent.

For example see CMOS NAND gate

Keywords : CMOS, Digital, Circuit, Gate, Making Gate, Create, Inverter, Circuit, Using, IGFET
Writer : delon  |
26 Nov 2006 Mon   
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