The OR function may be built up from the basic NOR gate with the addition of an inverter stage on the output:

Since it appears that any gate possible to construct using TTL technology can be duplicated in CMOS, why do these two "families" of logic design still coexist? The answer is that both TTL and CMOS have their own unique advantages.


First and foremost on the list of comparisons between TTL and CMOS is the issue of power consumption. In this measure of performance, CMOS is the unchallenged victor. Because the complementary P- and N-channel MOSFET pairs of a CMOS gate circuit are (ideally) never conducting at the same time, there is little or no current drawn by the circuit from the Vdd power supply except for what current is necessary to source current to a load. TTL, on the other hand, cannot function without some current drawn at all times, due to the biasing requirements of the bipolar transistors  from which it is made.

There is a caveat to this advantage, though. While the power dissipation of a TTL gate remains rather constant regardless of its operating state(s), a CMOS gate dissipates more power as the frequency of its input signal(s) rises. If a CMOS gate is operated in a static (unchanging) condition,  it dissipates zero power (ideally). However, CMOS gate circuits draw transient current during every output state switch from "low" to "high" and visa-versa. So, the more often a CMOS gate switches
modes, the more often it will draw current from the Vdd supply, hence greater power dissipation at greater frequencies.

A CMOS gate also draws much less current from a driving gate output than a TTL gate because  MOSFETs are voltage-controlled, not current-controlled, devices. This means that one gate can drive many more CMOS inputs than TTL inputs. The measure of how many gate inputs a single  gate output can drive is called fanout.

Another advantage that CMOS gate designs enjoy over TTL is a much wider allowable range of power supply voltages. Whereas TTL gates are restricted to power supply (Vcc) voltages  between 4.75 and 5.25 volts, CMOS gates are typically able to operate on any voltage between 3 and 15 volts! The reason behind this dispaity in power supply voltages is the respective bias requirements of MOSFET versus bipolar junction transistors. MOSFETs are controlled exclusively by gate oltage (with respect to substrate), whereas BJTs are current-controlled devices. TTL gate circuit esistances are precisely calculated for proper bias currents assuming a 5 volt regulated power suply. Any significant variations in that power supply voltage will result in the transistor bias currents eing incorrect, which then results in unreliable (unpredictable) operation. The only effect that ariations in power supply voltage have on a CMOS gate is the voltage definition of a "high" (1) tate. For a CMOS gate operating at 15 volts of power supply voltage (Vdd), an input signal must e close to 15 volts in order to be considered "high" (1). The voltage threshold for a "low" (0) signal emains the same: near 0 volts.

Keywords : Nand, Gate, Cmos, OR, CMOS-OR Gates, Logic Gate, Create, High, Low, Logic
Writer : delon  |
26 Nov 2006 Mon   
No Comments