Integrated Circuits ==>


This is ripple counter so beware that glitches may occur in any logic gate systems connected to their outputs due to the slight delay before the later counter outputs respond to a clock pulse.

The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.

NC = No Connection (a pin that is not used). # on the 7490 pins 6 and 7 connect to an
internal AND gate for resetting to 9.

For normal use connect QA to clockB and connect the external clock signal to clockA

The counter is in two sections: clockA-QA and clockB-QB-QC-QD. For normal use connect QA to clockB to link the two sections, and connect the external clock signal to clockA.

For normal operation at least one reset0 input should be low, making both high resets the counter to zero (0000, QA-QD low). Note that the 7490 has a pair of reset9 inputs on pins 6 and 7, these reset the counter to nine (1001) so at least one of them must be low for counting to occur.

Counting to less than the maximum (9 or 15) can be achieved by connecting the appropriate output(s) to the two reset0 inputs. If only one reset input is required the two inputs can be connected together. For example: to count 0 to 8 connect QA (1) and QD (8) to the reset inputs.

Connecting ripple counters in a chain: please see 74393

Keywords : 74xx, 74LSXX, 74HCxx, 74HCTxx, Integrated, Circuit, Ic, Pinout, Connection, Gate, Quad, Input, Output, Pals, 7490, Counter, GATE
Writer : delon  |
20 Mar 2006 Mon   
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