EECON1 Register

EECON1 register at address 88h is a control register with five implemented bits. Bits 5, 6 and 7 are not used, and by reading always are zero. Interpretation of EECON1 register bits follows:

EECON Register

bit 0  RD (Read Control bit)

Setting this bit initializes transfer of data from address defined in EEADR to EEDATA register. Since time is not as essential in reading data as in writing, data from EEDATA can already be used further in the next instruction.

1=initializes reading

0=does not initialize reading

bit 1 WR (Write Control bit)

Setting of this bit initia/izes writing data from EEDATA register to the address specified trough EEADR register.

1=initia/izes writing

0=does not initialize writing

bit 2 WREN (EEPROM Write Enable bit)

Enables writing to EEPROM

If this bit was not set, microcontroller would not allow writing to EEPROM.

1=writing allowed

0=writing disallowed

bit 3 WRERR (Write EEPROM Error Flag)

Error during writing to EEPROM

This bit was set only in cases when writing to EEPROM had been interrupted by areset signal or by running out of time in watchdog timer (if it´s activated).

1=error occured

0=error did not occur

bit 4 EEIF (EEPROM Write Operation Interrupt Flag bit)

Bit used to inform that writing data to EEPROM has ended.

When writing has terminated, this bit would be set automatically. Programmer must clear EEIF bit in his program in order to detect new termination of writing.

1=writing terminated

0=writing not terminated yet, or has not started.

Keywords : Pic EECON1 Register
Writer : delon  |
3 Mar 2006 Fri   
No Comments