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Logical Electronic

CMOS NAND Gate

CMOS NAND gate

CMOS NAND gate

Notice how transistors Q1 and Q3 resemble the series-connected complementary pair from the inverter circuit. Both are controlled by the same input signal (input A), the upper transistor turning off and the lower transistor turning on when the input is "high" (1), and visa-versa.

Notice also how transistors Q2 and Q4 are similarly controlled by the same input signal (input B), and how they will also exhibit the same on/off behavior for the same input logic levels. The upper transistors of
both pairs (Q1 and Q2) have their source and drain terminals paralleled, while the lower transistors
(Q3 and Q4) are series-connected.

 

What this means is that the output will go "high" (1) if either top transistor saturates, and will go "low" (0) only if both lower transistors saturate. The following sequence of illustrations shows the behavior of this NAND gate for all four possibilities of input logic levels (00, 01, 10, and 11):

 


Keywords : Nand, Gate, Cmos, Create, High, Low, Logic
Writer : delon  |
26 Nov 2006 Mon   
|  11.762 Views
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