dual decade (0-9) ripple counter
The 74390 contains two separate decade (0 to 9) counters, one on each side of the chip. They are ripple counters so beware that glitches may occur in any logic gate systems connected to their outputs due to the slight delay before the later counter outputs respond to a clock pulse.
For normal use connect QA to clockB and connect the external clock signal to clockA.
The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.
Each counter is in two sections: clockA-QA and clockB-QB-QC-QD. For normal use connect QA to clockB to link the two sections, and connect the external clock signal to clockA.
For normal operation the reset input should be low, making it high resets the counter to zero (0000, QA-QD low).
Counting to less than 9 can be achieved by connecting the appropriate output(s) to the reset input, using an AND gate if necessary. For example: to count 0 to 7 connect QD (8) to reset, to count 0 to 8 connect QA (1) and QD (8) to reset using an AND gate.
Connecting ripple counters in a chain: please see 74393.